Bandwidth per edge area, not bits per wafer, is the key metric

Switching accelerators from HBM to commodity DDR to save wafers fails because chip I/O escapes only on the edges; an HBM4 stack delivers ~2.5 TB/s per ~13mm shoreline versus only ~64-128 GB/s for DDR in the same area—an order of magnitude less bandwidth—and since FLOPS are gated by feeding weights and KV cache, the metric that matters is bandwidth per wafer edge, not bits per wafer.